SiC (silicon carbide) is a kind of wide band gap semiconductors similar to GaN or diamond. Having high heat and chemical resistance and excellent mechanical strength, SiC has been attracting attention as a semiconductor material operable in a severe environment, such as a high temperature environment, that precluded the use of conventional Si semiconductors. In recent years, there has been an increasing demand for a single crystal SiC substrate for use in high-frequency, high-voltage resistant electronic devices.
Production of a single crystal SiC substrate includes slicing an SiC single crystal ingot into wafers, grinding the as-cut wafer to a predetermined thickness using, e.g., a grinder, lapping the wafer with abrasive grains, e.g., of diamond, and polishing the lapped, wafer with finer abrasive grains to provide a mirror finish.
The production involves the step of removing a work damaged layer resulting from the grinding or lapping steps from the surface of the substrate. In order to remove the damaged, layer, it has been a practice generally followed to perform chemical mechanical polishing (CMP) using colloidal silica as abrasive grains.
If there is a defect, such as a damaged layer, on the surface of a single crystal SiC substrate on which an epitaxial thin film is to be formed, it would be difficult to well accomplish epitaxial growth, making it hard to provide an epitaxial substrate with desired characteristics and reliability. Therefore, it has been a practice to remove the damaged layer by chemical mechanical polishing (CMP) using colloidal silica abrasive grains as described in Patent Literature 1. A damaged layer is said to be present from the substrate surface to a depth of several hundreds of nanometers. Under the present circumstances, a long time is needed to achieve the CMP treatment because of the low polishing rate of colloidal silica abrasive grains.
In order to securely remove the damaged layer, it has been proposed to perform vapor phase etching in combination with a CMP treatment as disclosed in Patent Literatures 2 and 3. Patent Literature 4 proposes a process for producing an SiC epitaxial substrate including polishing a single crystal SiC substrate until the disturbed lattice layer is reduced to 3 nm or thinner, cleaning the polished, substrate at a high temperature in a hydrogen atmosphere, and epitaxially growing a thin film of silicon carbide on the cleaned substrate.
Cases are sometimes met with in which even a single crystal SiC substrate having been CMP treated for a long period of time fails to form a satisfactory epitaxial thin film. This has caused a reduction in yield of production of electronic devices involving formation of an epitaxial thin film. To perform vapor phase etching as in Patent Literatures 2 and 3 makes the production process complicated, which hinders efficient production of an epitaxial substrate.
The technique of Patent Literature 4, in which the disturbed lattice layer on the surface of a single crystal SiC substrate is removed as much as possible by polishing before the formation of an epitaxial thin film of silicon carbide, is thought to provide a high quality-epitaxial thin film. Reduction of the disturbed lattice layer on the surface of a single crystal SiC substrate assuredly seems to result in removal of the damaged layer. And yet, it is still considered that there is a room for farther investigation into factors other than the disturbed lattice layer on a polished single crystal SiC substrate in order to form a more defect-free, high-quality epitaxial thin film.
Non-Patent Literatures 1 and 2 report that a CMP treatment of an SiC substrate with an alkaline slurry containing MnO2 and MnO4− accelerates oxidation reaction, resulting in an improved, processing rate. The reports, however, are silent on the possibility of obtaining an SiC substrate with a highly precisely polished surface to a conventionally unreachable level by performing a CMP treatment under a specific condition.